The present invention relates to a semiconductor device, such as a random access memory (RAM), particularly a word line configuration of a memory cell array therein.
An example of a DRAM (dynamic RAM) is shown in IEEE Journal of Solid State Circuits, Vol. SC-20, No. 5, Oct. 1985, pp. 903-907, particularly FIG. 1 in page 904, therein.
The DRAM comprises a plurality of memory cells arranged in a matrix, a plurality of bit lines for transferring data in and out of the memory cells, and a plurality of word lines intersecting orthogonally with the bit lines for selecting the memory cells.
The word lines are selectively raised to a high potential to enable writing and reading of data in and out of the memory cells connected to the selected word line.
The operating speed in writing and reading is an important factor determining the performance of the DRAM. The resistance of the bit lines and the word lines should therefore be small.
In the above-referenced publication, the bit lines are made of a polycide layer (combination of polysilicon layer and silicide layer stacked on it), while the word lines are made of a polysilicon layer and a separate aluminum layer. More specifically, main word lines are formed of the polysilicon layer and auxiliary word lines are formed of the aluminum layer. The auxiliary word lines extend over and along the main word lines and connected with the main word lines by contacts provided at certain intervals.
The above-described configuration of the word lines has the following problems, which will be explained with reference to FIGS. 1, 2 and 3.
FIG. 1 shows a chip architecture of an example of DRAM. The chip surface comprises an area 21 for a row decoder, an area 22 for a column decoder and sense amplifiers, and areas 23 for blocks of memory cell array. In the illustrated example, the memory cell array is divided into four blocks. Only one of a plurality of word lines 24 and only one of a plurality of bit lines 25 are illustrated.
FIGS. 2 and 3 show how the word lines 24 are configured relative to a substrate 31. As illustrated, each of the word lines 24 is made up of a main word line 34 (shown in solid line) and an auxiliary word line 34' (shown in dashed line) which is connected with the main word line 34 by means of contacts 36 formed at intervals.
As will be seen from FIGS. 2 and 3, the minimum width that can be achieved for the auxiliary word lines, which are formed of aluminum is larger than the minimum width that can be achieved for the main word lines formed of polysilicon. The spaces between the aluminum word lines must also be made larger to prevent short-circuitry. This is due to the fact that aluminum has larger grain size and also needs to be thicker than polysilicon, so that it is more difficult to realize fine pattern with aluminum than with polysilicon. Furthermore, hillocks develop relatively easily on aluminum, so that short-circuiting occurs more easily with aluminum lines. For instance, while the width and the space of the main word lines 34 can be made at 0.8 micrometers, auxiliary word lines must have a width of 1 micrometer and a space of 1.5 micrometers. That is, while the main word lines 34 can be made to a pitch of 1.6 micrometers, the auxiliary word lines 34' need to have a minimum pitch of 2.5 micrometers. Since the main word lines 34 and the auxiliary word lines 34' are used in pairs, the degree of integration is limited by the pitch of the auxiliary word lines 34'.
To overcome this problem it can be conceived to use a polycide layer in place of the polysilicon layer for the main word line 34 and eliminate the auxiliary word line 34'. The polycide layer has a resistance one order smaller than the polysilicon layer, but the sheet resistivity of the polycide is 2-3.OMEGA./.quadrature., for example. This will place a limit to the maximum length of the word line 34 that can be used. Because of the limit in the length of the word line 34, it may become necessary to increase the number of the blocks of 23 memory cell array. For instance, the memory cell array may be divided into eight blocks rather than four blocks as shown in FIG. 1. But when the number of blocks is increased, additional decoders are needed. As a result, the chip size is increased.